1. The Field of the Invention
The present invention relates to removing doped silicon dioxide from a structure in a process that is selective to undoped silicon dioxide. More particularly, the present invention is directed to a method of using a high density plasma etcher such that doped silicon dioxide is removed from a structure at a material removal rate that is greater than that of undoped silicon dioxide.
2. The Relevant Technology
Modem integrated circuits are manufactured by an elaborate process in which a large number of electronic semiconductor devices are integrally formed on a semiconductor substrate. In the context of this document, the term xe2x80x9csemiconductor substratexe2x80x9d is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure including but not limited to the semiconductive substrates described above. The term xe2x80x9cdoped silicon dioxidexe2x80x9d refers to silicon dioxide having a dopant concentration greater than or equal to about 3% by weight. The term xe2x80x9cundoped silicon dioxidexe2x80x9d is defined as silicon dioxide having a dopant concentration less than about 3% by weight.
The semiconductor industry is attempting to increase the speed at which integrated circuits operate, to increase the density of devices on integrated circuits, and to reduce the price of integrated circuits. To accomplish this task, semiconductor devices, including capacitors, resistors, transistors, diodes, and the like, are continually being increased in number and decreased in dimension in a process known as miniaturization. In advanced manufacturing of integrated circuits, hundreds of thousands of these semiconductor devices are formed on a single semiconductor substrate. Efficient packing of these devices requires multilayer topographical design.
One common process for forming a topographical design on a semiconductor substrate involves etching of semiconductor material. The dimensional extent of material removal during an etch process is typically controlled by providing etch-resistant materials in predetermined regions of a semiconductor substrate. An etch-resistant structure that shields underlying material from an etch is known as an etch mask, while etch-resistant material positioned beneath material to be removed is an etch stop. In either case, the etch process is substantially selective to the etch stop or etch mask, while being not selective to the material to be removed.
In one common etching process, an etch-resistant masking layer is deposited and patterned over the semiconductor material to be etched. The pattern formed on the layer of masking material defines a series of openings in the masking material and corresponds to the topographical design to be formed during the etching process. Next, an etchant is applied to the semiconductor material through the pattern openings. A material, which may be doped silicon dioxide, is removed through the pattern openings, while the etch mask protects material positioned directly therebelow. Currently, photoresist material is commonly used as an etch mask. Use of photoresist material in an etch process involves forming, developing, and patterning the photoresist material, applying an etchant to etch the silicon dioxide, and then removing the photoresist material. The multiple steps involved in using photoresist material require time and resources that can increase the cost of producing integrated circuits.
In other applications, an etch-resistant material, such as silicon nitride is commonly used as an etch stop or etch mask material, particularly in connection with etch processes of silicon dioxide with a fluorinated etch chemistry. For example, in a conventional self-aligned etch process for forming a contact opening to an underlying active region on a semiconductor substrate, silicon nitride is usually used on top of a gate stack as an etch stop. The silicon nitride cap prevents overetching and ensures that the resulting contact hole is aligned directly atop the active region.
One of the problems in the prior art with forming a silicon nitride cap is the simultaneous formation of a silicon nitride layer on the back side of a semiconductor wafer. The particular problems depend on the process flow. For instance, where a low pressure chemical vapor deposition is used to deposit silicon nitride, both sides of the semiconductor wafer would receive deposits of silicon nitride. The presence of silicon nitride on the back side of the semiconductor wafer causes stress which deforms the shape of the semiconductor wafer, and can also potentially cause deformation of the crystal structure as well as cause defects in the circuit. Additionally, silicon nitride deposition is inherently a dirty operation having particulate matter in abundance which tends to reduce yield. When a low pressure chemical vapor deposition process is utilized, the silicon nitride layering on the back side of the semiconductor wafer must be removed later in the process flow.
It would be advantageous to have a method for providing an etch mask material that does not require removal after the etching is completed. Further, it would be an advancement in the art to provide an alternative to silicon nitride for use as an etch stop in self-aligned contact formation.
The present invention relates to etching doped silicon dioxide from a structure in a process that is selective to undoped silicon dioxide. According to the invention, a structure is provided having a first region substantially composed of doped silicon dioxide and a second region substantially composed of undoped silicon dioxide. The first and second regions are configured to define a topographical structure to be formed by the selective etch process. A high density plasma system is used to remove doped silicon dioxide from the topographical structure.
A high density plasma system, as defined herein, has two electrodes. The two electrodes are the upper electrode and lower electrode. There is a space or gap between the two electrodes. The upper electrode is sometimes referred to as the upper window. An inductively coupled plasma is usually applied to the upper electrode (or upper window). Sometimes, the power that is applied to the upper electrode can be divided into two parts, such as an outer coil and an inner coil. The power that is applied to the upper electrode is usually referred to, and is referred to herein, as the source power.
A semiconductor substrate of a wafer being etched is situated on the lower electrode where an optional RF power is usually applied thereto. This power is usually referred as to the bias power. The etch under these condition has a plasma density not less than about 109 cmxe2x88x923, and the operating pressure is usually at 10 Millitorr (mT) or below.
A high density plasma source with a fluorinated etch chemistry is applied to the structure such that an inductively-coupled power is delivered to the upper electrode in an amount less than about 1000 Watts (W) per 200 mm-diameter wafer surface. Stated otherwise, the source power density can be expressed as an amount less than about 0.032 W/mm2 or 19.89 W/in2. Accordingly, doped silicon dioxide is removed from the structure at a material removal rate that is greater than the rate of removal of undoped silicon dioxide.
In a reactive ion etcher (RIE), only the bottom electrode where the wafer is situated is powered. Thus, the bottom electrode is preferably the same size as the wafer. As such, the power density is defined as the ratio between the power and the wafer surface area. In a high density etcher, however, the source power which generates a plasma in the etcher is applied to the upper electrode or upper window. A coil is situated on the upper window. There is generally no definite shape or size of the coil that sits on the upper window and the size or volume of the plasma zone is not necessarily the same as the size of the coil. As such, the power density is defined as the source power applied to the upper window over the surface area of the wafer situated upon the bottom electrode.
The method of the invention extends to any structure from which doped silicon dioxide may be removed selectively to undoped silicon dioxide. The invention has been found particularly advantageous for use in semiconductor structure fabrication. In one embodiment, a doped silicon dioxide layer is formed over a semiconductor substrate. An undoped silicon dioxide layer is then formed over the doped silicon dioxide and patterned to provide one or more openings therein extending to the doped silicon dioxide layer. The high density plasma etch process described above is conducted, thereby selectively removing doped silicon dioxide through the openings in the pattern and forming a predetermined topographical structure. The undoped silicon dioxide layer acts as an etch mask during the etching process. Under this embodiment, the undoped silicon dioxide etch mask does not need to be removed after the etching process is completed.
According to another embodiment of the invention, the positions of the doped and the undoped silicon dioxide layers within the structure are reversed. The undoped silicon dioxide layer is formed over the semiconductor substrate, with the doped silicon dioxide layer formed thereupon. Photoresist is deposited and patterned on doped silicon dioxide to provide openings. The high density plasma etch is directed onto the structure, thereby removing doped silicon dioxide to form an opening that terminates at the undoped silicon dioxide layer.
The invention is useful with a variety of applications wherein doped silicon dioxide is etched from a semiconductor structure. For example, undoped silicon dioxide layers may be positioned both over and under a doped silicon dioxide layer. Alternatively, the invention may be used for forming a self-aligned contact hole to a contact surface on a semiconductor substrate. The self-aligned contact hole is formed by first providing a multilayer structure over the semiconductor substrate that comprises a thin silicon dioxide layer, a layer of conductor material, and a refractory metal silicide layer. By way of example, the multilayer structure may include a gate oxide layer, a polysilicon layer, and a refractory metal silicide layer successively formed over a semiconductor substrate. An undoped silicon dioxide layer is then formed over the multilayer structure.
The multilayer structure is patterned to form the designated topography, with openings extending to the semiconductor substrate. Doped silicon dioxide is next formed over the semiconductor substrate. A patterned etch mask layer is utilized to expose selected portions of the doped silicon dioxide layer that are intended to be etched. One example of a topographical structure created utilizing this process are gate stacks. A high density plasma etch as described above is conducted to selectively and anisotropically remove doped silicon dioxide such that a self-aligned contact opening extends to a contact surface on the semiconductor substrate between the gate stacks.
As can be seen, the present invention provides undoped silicon dioxide as an alternative to silicon nitride that has previously been used in many selective etch processes. In other applications, the use of photoresist material that must be removed after etching is reduced or eliminated under the invention. Further, the etching process of the invention may be conducted with high density plasma etchers.